1. Field of the Invention
The present invention relates generally to integrated circuits and, more particularly, to an integrated circuit (chip) carrier with zones in the x-y plane of controlled coefficients of thermal expansion.
2. Background of the Invention
The reliability and performance of integrated circuit packages is enhanced by matching the coefficient of thermal expansion (CTE) of the printed circuit board and the semiconductor chip. Such a structure prevents discontinuous expansion during thermal cycling and its resultant stresses on the chip package components. Generally, however, a chip has a CTE of 2.7 ppm/C.degree. and the printed circuit board has a CTE of 10 to 25 ppm/C.degree.. This mismatch is especially a problem where ball grid array (BGA) interconnections and controlled collapse chip connector (C4, or "flip chip") technologies are used. Often, chip carriers are interposed between the chip and the circuit board; the CTE of the chip carrier is itself chosen as some intermediate value to provide a reasonable match to both the chip and to the printed circuit board.
In the progression of chip package technology development, as chip input-output (I/O) increased beyond the capabilities of peripheral lead devices, BGA interconnections and other soldered interfaces emerged as the solution. Where the CTE of the chip does not match the CTE of the circuit board, however, the footprint size of the BGA and C4 interconnections is limited because of stress-induced fatigue on the solder joints during thermal cycling.
Thermal cycling is encountered during normal circuit operation and, where the CTEs of the package components do not match, movement of the chip with respect to the circuit board results. The use of standard area array soldering to join the carrier to the board often provides an insufficient mechanical fatigue strength to mediate a significantly different expansion of the two materials. Consequently, under conditions of thermal cycling, the solder joints break, disrupting the circuit operation and necessitating repair.
To strengthen the carrier-to-substrate bond, attempts were made to increase the diameter of the connection, thus rendering the bond connection more compliant. When this is done, however, pin out density is decreased dramatically. For example, when similar materials are used for the carrier and board, a contact area of 0.25 mm (10 mils) with a gap between contacts of 0.25 mm (10 mils) provides a contact array having a 0.50 mm (20 mils) pitch. When dissimilar materials are used for the carrier and board, a 1.0 mm (40 mils) contact must be provided which results in a contact array having a 1.25 mm (50 mils) pitch. Such a decrease in pin out density is undesirable.
The use of heatsinks was another proposed solution to the problems with organic chip carriers and the related poor thermal conductivity associated with BGA technology. Heatsinks were employed to manage the thermal and power performance requirements of these packages, but the CTE mismatch still remained. Thus, although heat accumulation was decreased, mechanical failure within the chip due to stress and cracking still existed.
Some partial solutions to the above problems eventually emerged. One solution was to provide a separate connection system to relieve the CTE mismatch. Such connection systems included flex cables or sockets. Most of the past solutions employed some type of interface between the chip and the printed circuit board. The material for the interface was selected such that it had an intermediate CTE within the CTE range of both the chip and board.
Thus, FIG. 1A depicts a wirebond BGA package, where a baseplate 10 (CTE of 17 ppm/C.degree.) would be provided with a CTE near that of the printed circuit board 20 (CTE of 20 to 25 ppm/C.degree.). The chip 30 has a CTE of about 2 ppm/C.degree.. Thus, the baseplate 10 would provide an intermediate match to the printed circuit board 20 and the chip 30. It is more important that the baseplate 10 come close to matching the printed circuit board, because the thermally induced stresses increase directly with the overall size of the mismatched interface. For this type of structure, the overall size of the BGA array is always larger than the chip size. Furthermore, the wirebond interconnections 26 are somewhat compliant, as is the adhesive 36 connecting the chip to the baseplate. Also illustrated in FIG. 1A are the solder balls 22, which connect the circuitry (not shown in FIG. 1A) on the surface of the baseplate 10 to the printed circuit board 20 and the molding compound or encapsulant 24 which encapsulates chip 30.
FIG. 1B shows a C4 flip chip BGA package, where a chip 30 (about 2 ppm/C.degree.) is connected using C4 solder balls 42 to a baseplate 10. The C4 interconnections are reinforced with an encapsulant 36. The C4's are connected to the BGA balls 22 with circuitry (not shown) on the baseplate 10. The BGA balls 22 connect to the printed circuit board 20. This type of package offers more dense interconnections than the package shown in FIG. 1A, but the C4 connections are less compliant than wirebond connections, thus requiring a closer match in CTE between the chip 30 and the baseplate 10.
The partial solutions illustred in FIGS. 1A and 1B can be optimized to provide the best possible compromise of CTEs among the various components. When the temperature of the package increases during operation, however, the printed circuit board 20 expands the most, the chip 30 expands the least, and the baseplate 10 expands at some intermediate value. Although it is intended for intermediate expansion of the baseplate 10 to reduce the thermal stress, it is not eliminated. As the array size of the BGA interconnections grows, and as the chip size increases, the CTE mismatch becomes increasingly problematic, resulting in reliability and performance problems.
Another proposed solution is to have a carrier with a CTE varying in the z-plane (where z is the thickness). This proposed solution matches the CTE of the chip on one side of the baseplate and the CTE of the printed circuit board on the other side of the baseplate. This layered baseplate, however, causes warping during processing because each layer expands at a different rate. Thus, the problem of preventing BGA and C4-ball shear and chip cracking remains unsolved.
Other alternatives include full compensation planes and chip encapsulation. These alternatives tend, however, to restrict the size of the chip carrier. Still another proposed solution is to incorporate low CTE materials such as INVAR (INVAR is a registered trademark of Creusot-Loire used in connection with a steel alloy containing 36% nickel) or quartz into the laminate. If the overall CTE is lowered too much, however, BGA failure results. And chip cracking and C4 failure can result if the CTE is not lowered enough. Therefore, this proposed solution also has drawbacks and there remains a need for a chip package which removes the stresses caused by inconsistent expansion during thermal cycling.
To overcome the CTE shortcomings of conventional integrated circuit chip packages, a new integrated circuit chip package is provided. An object of the present invention is to provide a package with improved CTE matches between the chip and carrier and between the carrier and the printed circuit board. A related object is to improve these CTE matches in BGA applications. Another object is to reduce thermal stress, and resulting defects, without limiting the size of the chip or chip carrier. Yet another object of the present invention is to provide a package which minimizes warping.